1. Field of the Invention
The present invention relates to a test apparatus configured to test a device under test.
2. Description of the Related Art
In a testing operation for a semiconductor integrated circuit (which will be referred to as the “DUT” hereafter) that employs CMOS (Complementary Metal Oxide Semiconductor) technology such as a CPU (Central Processing Unit), DSP (Digital Signal Processor), memory, or the like, electrical current flows in a flip-flop or a latch included in the DUT while it operates receiving the supply of a clock. When the clock is stopped, the circuit enters a static state in which the amount of current decreases. Accordingly, the sum total of the operating current (load current) of the DUT changes over time depending on the content of the test operation, and so forth. Also, various kinds of analog circuits and various kinds of analog/digital hybrid circuits also have a problem of such a fluctuation in the operating current.
A power supply circuit configured to supply electric power to such a DUT has a configuration employing a regulator, for example. Ideally, such a power supply circuit is capable of supplying constant electric power regardless of the load current. However, in actuality, such a power supply circuit has an output impedance that is not negligible. Furthermore, between the power supply circuit and the DUT, there is an impedance component that is not negligible. Accordingly, the power supply voltage fluctuates due to fluctuation in the load.
[Related Art Documents]
[Patent Documents]
[Patent Document 1]
Japanese Patent Application Laid Open No. 2007-205813
[Patent Document 2]
International Publication WO 2010/029709A1 pamphlet
Typically, it is rare for the power supply performance (power integrity) of a power supply circuit mounted on a test apparatus to match that of a power supply circuit employed in an environment in which the DUT is actually operated, i.e., in an environment for a set on which the DUT is to be mounted (actual equipment environment or user environment). Accordingly, there is a difference in the waveform of the power supply voltage supplied to the DUT between the user environment and an environment used in the test (tester environment). This leads to a problem in that the quality (pass/fail) judgment result obtained in the tester environment does not match the quality judgment result obtained in the user environment. Such a problem will also be referred to as “divergence in the test results”.
FIGS. 1A through 1C are diagrams for describing the divergence in the test results. In each of FIGS. 1A through 1C, the left-side diagram shows the power supply voltage waveform, and the right-side diagram shows a histogram. In the histogram, the horizontal axis represents a predetermined device characteristic of a semiconductor circuit. Examples of such a characteristic value include propagation delay. FIG. 1A shows the test result obtained in the user environment. FIG. 1B shows the test result obtained in a tester environment having a lower quality than that of the user environment. FIG. 1C shows the test result obtained in a tester environment having a higher quality than that of the user environment.
The limit value LMT in FIGS. 1A through 1C corresponds to a threshold value used in the quality judgment. In this case, the device characteristic values plotted on the left side of the limit value are each determined as “pass”. On the other hand, the device characteristic values plotted on the right side of the limit value are each determined as “fail”. However, as shown in FIG. 1B, in a case of performing the quality judgment in a tester environment having a lower quality than that of the user environment, DUTs to be judged as “pass” in the desired test are judged as “fail”. This leads to yield loss (overkill).
Conversely, as shown in FIG. 1C, in a case of performing the quality judgment in a tester environment having a higher quality than that of the user environment, DUTs to be judged as “fail” in the desired test are judged as “pass”. This leads to a problem of test escape (underkill).